1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device in which only a single surface of a substrate is sealed with resin, and a semiconductor device thus fabricated. More particularly, the present invention relates to a method of fabricating a semiconductor device used in a stacked-type semiconductor device having a plurality of packages stacked.
2. Description of the Related Art
Recently, portable electronic devices such as cellular phones and non-volatile storage media such as IC memory cards have been downsized and it has been required to reduce the number of parts used in the electronic devices and storage media and to downsize these parts.
It is thus desired to efficiently package semiconductor elements or chips, which are major components among the parts of the electronic devices. A stacked-type package in which a memory-use package and a logic-use package are stacked is known as one of the packages that meet the above desire. Documents 1 through 3 disclose methods of fabricating stacked-type packages; Patent Document 1: Japanese Patent Application Publication No. 8-236694; Patent Document 2: Japanese Patent Application Publication No. 2003-218273; and Patent Document 3: Japanese Patent Application Publication No. 6-13541.
An example of the stacked-type packages is shown in FIG. 1. The stacked-type package shown in FIG. 1 has a first semiconductor device 110 on which a second semiconductor device 120 is stacked. The first semiconductor device 110 has a semiconductor chip that is mounted on an interposer 111 and is not shown. The semiconductor chip is sealed with a sealing material 112. Solder balls 113 for making an electrical connection with another substrate are provided on the backside of the interposer 111. Similarly, the second semiconductor device 120 has a semiconductor chip that is mounted on an interposer 121 and is not shown. The semiconductor chip is sealed with a mold resin 122. Solder balls 123 are provided on the backside of the interposer 121.
FIG. 2A shows top and cross-sectional views of a first structure of the first semiconductor device 110, and FIG. 2B shows top and cross-sectional views of a second structure thereof. As shown in FIGS. 2A and 2B, electrode pads 114 for making an electrical connection with the solder balls 123 of the second semiconductor device 120 are provided on the interposer 111 of the first semiconductor device 110. When the second semiconductor device 120 is stacked on the first semiconductor device 110, the solder balls 123 of the second semiconductor device 120 are aligned with the electrode pads 114 of the first semiconductor device and are brought into contact therewith, so that the first semiconductor device 110 and the second semiconductor device 120 are electrically connected.
A description will now be given of a method of sealing the semiconductor chip of the first semiconductor device 110 with the sealing material 112. As shown in FIG. 1, the first and second semiconductor devices 110 and 120 are sealed with the sealing materials 112 and 122 in order to protect the semiconductor devices from a shock and scratch. The molding of resin is generally implemented by transfer molding. In the transfer molding, at the time of molding the sealing material 112 on the rigid interposer 111 that is typically a glass epoxy substrate, the interposer 111 is placed in molds 130 and is clamped, as shown in FIG. 3. In the molds 130, there are formed a gate 131 that is a passage of injected resin and a cavity 132 in which resin is injected. The resin is supplied to the cavity 132 via the gate 131 and is provided around the semiconductor chip.
As shown in FIG. 2A, a gold plating portion 115 that has a poor adhesiveness to the sealing material is formed at a single corner of the interposer 111 on which the gate serving as the passage of resin is provided. The gold plating portion 115 is provided on the interposer 111 in order to remove the resin on the gate after the resin is molded.
In a case where a small number of electrode pads 114 is provided on the interposer 111, the gate 116 may be positioned outside of the interposer 111 in which a large area for forming the sealing material 112 is provided on the interposer 111, as shown in the conventional second structure of the first semiconductor device 110 shown in FIG. 2B. In contrast, as shown in the conventional first structure of the first semiconductor device 110 shown in FIG. 2A, the gate is inevitably provided on the interposer 111 in a case where the area for forming the sealing material 112 is made small and the electrode pads 114 are arranged so as to surround the sealing material in order to use an increased number of electrode pads 114. Thus, the corner of the interposer 111 is not provided with the electrode pads 114 but the gold plating portion 115.
However, the above-mentioned transfer molding has a disadvantage in that fat and oil and powder dusts such as resin burrs may adhere to the interposer 111 and the electrode pads 114 may be contaminated because the interposer 111 is placed in the molds 130 without any processing and is sealed with the sealing material. This affects the bondability of the semiconductor devices and degrades the production yield.
The presence of the gold plating portion 115 shown in FIG. 2A does not allow the electrode pads 114 to be arranged in the area of the gold plating portion 115 on the interposer 111. Thus, the interposer 111 is required to have a larger size to compensate for the lost electrode pads 114. The user of the larger size prevents downsizing of the semiconductor device.
A molding process of a top gate type has been proposed to overcome the above disadvantage, in which the sealing material is provided from the upper side of the semiconductor chip. However, this process has the following disadvantages. First, it is difficult to remove a remaining gate portion and a remaining runner portion after molding. Second, it is necessary to clean up the molds each time the molds are used because an inlet for injection of resin is small. Third, the molds are complicated and are thus expensive.